It is often desirable to add or reduce delay to a clock line with respect to a data line to improve the timing margins. In such case, instead or purposely minimizing skew, we change our objective to add additional delay in the clock line with respect to the data line. To be able to do this we must have a good understanding of the set up and hold timing models of the receiver section of the circuit. We should also have an understanding of the timing relationship at the driver side. If the simulation shows an improvement in the timing margin by use of clock or data line delay adjustment, we can implement it at the PCB design level.
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